发明名称 Gate array architecture
摘要 Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: a gate array architecture. The gate array architecture includes at least one base site, the at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with another embodiment of the invention, a method of fabricating an integrated circuit chip includes: processing a semiconductor substrate to form a gate array architecture of transistors in the substrate. The gate array architecture includes at least one base site being three tracks wide and including four N-type transistors and four P-type transistors. Briefly, in accordance with still another embodiment of the invention, an article includes: a storage medium, the storage medium having instructions stored thereon, the instructions, when executed, resulting in the capability to design the layout of an integrated circuit chip for fabrication, the integrated circuit chip including a gate array architecture, the gate array architecture including at least one base site being three tracks wide and including four N-type transistors and four P-type transistors.
申请公布号 US2001045846(A1) 申请公布日期 2001.11.29
申请号 US20010912639 申请日期 2001.07.24
申请人 AKSAMIT RANDY J. 发明人 AKSAMIT RANDY J.
分类号 H01L27/02;H01L27/118;(IPC1-7):H03K19/00 主分类号 H01L27/02
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