| 摘要 |
A class D amplifier includes a separating circuit for separating a pulse code modulation (PCM) signal into a K least significant bits (LSBs) signal and an L most significant bits (MSBs) signal; a PCM to pulse width modulation (PWM) converter for converting the L MSBs signal into a PWM signal; and an LSB processor for proportionally altering the PWM signal from the PCM to PWM converter based upon the K LSBs signal to define a PWM output control signal. The PCM input signal may be an N-1 bit PCM magnitude signal. The amplifier includes a sign and magnitude extraction circuit for extracting a sign bit signal and the N-1 bit magnitude signal from an N bit two's complement PCM input signal. The class D amplifier also includes a switch driver responsive to the extracted sign bit signal and the PWM output control signal, such as to control polarity and on time, respectively. The PCM to PWM converter may be one of a symmetric PCM to PWM converter; a trailing edge PCM to PWM converter; and a leading edge PCM to PWM converter. |
