| 摘要 |
An apparatus includes a mixed signal application-specific integrated circuit (ASIC) (112), which is comprised of an analog-to-digital converter (A/D) as an input circuit, an internal digital delay circuit, and a digital-to-analog converter (D/A) as an output circuit. Formation of receive beams are accomplished by a plurality of mixed signal ASICs (112A-112N), low pass filters (120A-120N) and analog combiners (104), which combine a plurality of low pass filtered and time delayed analog signals located at the outputs of a plurality of mixed signal ASICs (112A-112N). Formation of transmit beams are accomplished by a plurality of analog splitters, mixed signal ASICs and low pass filters which distribute low pass filtered and time delayed analog signals to a plurality of subarrays in an array antenna. The design of the digital delay unit is intended to provide true time delays, with a delay increment equal to a fraction of the period of the digital clock that drives the digital delay unit.
|
