发明名称 |
LOW LATENCY SHARED MEMORY SWITCH ARCHITECTURE |
摘要 |
A method and apparatus are presented for operating a time slicing shared memory switch. The apparatus includes a bus for receiving a plurality of data frames in a respective plurality of input channels to the switch. A slice crosspoint applies the plurality of data frames to a shared memory in a time sliced manner. The time slice is established for each section of a shared memory to be staggered so that on any clock cycle, one memory portion is being accessed for writing at least some of the data frames and on a next clock cycle the memory portion is accessed for reading at least a portion of the data.
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申请公布号 |
US2001046235(A1) |
申请公布日期 |
2001.11.29 |
申请号 |
US19990475016 |
申请日期 |
1999.12.30 |
申请人 |
TREVITT STEPHEN;GRANT ROBERT HALE;BOOK DAVID |
发明人 |
TREVITT STEPHEN;GRANT ROBERT HALE;BOOK DAVID |
分类号 |
G06F12/00;H04J3/00;H04L12/56;H04Q11/04;(IPC1-7):H04L12/28 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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