FPGA with configurable clock lines

摘要

A field programmable gate array (FPGA) is disclosed, comprising a matrix of rows and columns of programmable logic cells (11) interconnectable to each other and to input and output terminals of the circuit, each logic cell including at least one synchronous element therein responsive to a clock signal, and a set of clock lines (CK0 - CK7) including at least one main clock line receiving a clock signal, a plurality of column clock lines connectable to said at least one main clock line and each associated with a particular column of logic cells (11), and for each column clock line a plurality of sector clock lines (92) connectable to that column clock line, each sector clock line connected to and providing a clock signal to a subset of a column of logic cells (11).