发明名称 |
SYSTEM AND METHOD FOR PARALLEL DATA COMPRESSION AND DECOMPRESSION |
摘要 |
An integrated memory controller (IMC) including MemoryF/X Technology which includes data compression and decompression engines for improved performance. To improve latency and reduce performance degradations normally associated with compression and decompression techniques, the MemoryF/X Technology encompasses multiple novel techniques such as: 1) parallel lossless compression/decompression; 2) selectable compression modes such as lossless, lossy or no compression; 3) priority compression mode; 4) data cache Techniques; 5) variable compression block sizes; 6) compression reordering; and 7) unique address translation, attribute, and address caches. The parallel compression and decompression algorithm allows high-speed parallel compression and high-speed parallel decompression operation. <IMAGE> |
申请公布号 |
EP1157470(A1) |
申请公布日期 |
2001.11.28 |
申请号 |
EP20000905859 |
申请日期 |
2000.01.27 |
申请人 |
INTERACTIVE SILICON, INC. |
发明人 |
DYE, THOMAS, A.;ALVAREZ, MANUEL, J., II;GEIGER, PETER |
分类号 |
G06F12/04;G06T9/00;H03M7/30;H03M7/40;H04N7/26;H04N7/50 |
主分类号 |
G06F12/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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