发明名称 |
Efficient half-cycle clocking scheme for self-reset circuit |
摘要 |
A pipelined domino architecture includes pairs of pipeline stages each comprising a first active clocked stage and a number of subsequent self-reset logic gates. Each pipeline stage is clocked by one or the other of a clock signal. Each active clocked stage and self-reset logic gate of any particular pipeline state includes a reset circuit to reset the output of such stage or gate at the conclusion of an evaluation period that is initiated by a phase of the clock signal. Only the active clocked stage is clocked; the self-reset logic stages rely upon the reset of the output of the active clocked stage to generate the necessary reset signals that will reset their respective outputs.
|
申请公布号 |
US6323688(B1) |
申请公布日期 |
2001.11.27 |
申请号 |
US20000520498 |
申请日期 |
2000.03.08 |
申请人 |
ELBRUS INTERNATIONAL LIMITED |
发明人 |
PODLESNY ANDREW V.;MALSHIN ALEXANDER V. |
分类号 |
H03K19/096;(IPC1-7):H03K19/096 |
主分类号 |
H03K19/096 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|