| 摘要 |
A semiconductor integrated circuit device which can save defect bits in an auxiliary storage portion functioning as a cache memory is provided. A redundant SRAM cell array MAR is provided so as to be adjacent to a SRAM cell array MA of a SRAM portion functioning as a cache memory, and with the positions of rows matching. Redundant cells which are alternatively selected based on redundant selection signals, are arranged in matrix form in this redundant SRAM cell array MAR. Moreover, a data input/output line SIOR is provided in each row of this SRAM cell array MAR, and each data input/output line SIOR is connected to a global data input/output line GIOR via a data input/output line connection circuit which is alternatively conduction controlled based on a predetermined selection signal. This global data input/output line GIOR is connected to a read/write bus line together with a read/write amplifier which is used at normal times.
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