Bit counter stage, particularly for memories

摘要

A bit counter stage, particularly for memory addresses, including: a master storage circuit; a slave storage circuit which is connected to the master storage circuit; a circuit for enabling the transit of an external address in the master storage circuit; a circuit for enabling the connection between the slave storage circuit and the master storage circuit; a circuit for enabling the connection between the master storage circuit and the slave storage circuit; a circuit for calculating the product of the external address and of an input carry signal which arrives from a preceding counter stage; and a circuit for calculating an output carry signal on the basis of the external address and of the input carry signal.