| 摘要 |
An efficient iterative, gridless, cost-based router for a computer controlled integrated circuit design. The fine routing process is used during the wire routing phase of an integrated circuit design and fabrication process. During the wire routing process, wires are routed between pins of nets. The routing process of the present invention is gridless and utilizes lanes that are defined based on the boundaries of objects. The cost-based router computes a cost for each wire path, and the cost is based on: (1) the manhattan wire distance: (2) the layers in which the wire runs; and (3) any overlap the wire has with soft obstacles (e.g., other wires, etc.); and (4) an estimated cost to the target. Cost computation is reduced by considering only obstacles within the layer in which a lane is run. The number of paths determined for a wire route is reduced by pruning possible paths based on the placement of obstacles within the integrated circuit. Further pruning is performed by picking the lowest cost child lane in cases when several lanes select the same lane. Paths are also pruned by stopping along any path whose work-in-progress cost estimation exceeds the final cost of a path already discovered. In multi-pin nets, the routing process selects that path (of equal cost paths) between a source pin and a target pin that also runs closer to another unconnected pin of the multi-pin net. When a source-target wire route is performed for a multi-pin net, the unconnected pin is treated as the target and the source is considered as the source-target wire route.
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