发明名称 DES cipher processor for full duplex interleaving encryption/decryption service
摘要 A full duplex DES cipher processor (DCP) supports to execute sixteen rounds of data encryption standard (DES) operation in four encryption modes and four decryption modes, namely: Electronic Code Book (ECB) mode, Cipher Block Chaining (CBC) mode, Cipher Feedback (CFB) mode, and Output Feedback (OFB) mode for both encryption and decryption. A DCP is composed of an I/O unit, an IV/key storage unit, a control unit, and an algorithm unit. The algorithm unit is used to encrypt/decrypt the incoming text message. The algorithm unit having a crypto engine allows encryption and decryption performed alternately, by sharing the same crypto engine. Since for crypto applications in communication services like T1, E1, V.35, the algorithm unit operation time is much shorter than the data I/O time; in other word, the algorithm unit is in the idle state mostly. The full duplex operation is achieved by storing the interim results of the DES encryption operation in a cipher text buffer (CTB) and the decryption results in a plain text buffer (PTB), where the CTB and PTB are in the crypto engine. The full duplex DCP has two ports, one for encrypting and the other for decrypting. In addition, the DCP can also be used for single port simplex or dual port simplex applications.
申请公布号 US6324286(B1) 申请公布日期 2001.11.27
申请号 US19980166671 申请日期 1998.10.05
申请人 INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE 发明人 LAI YI-SERN;CHUANG I-YAO;CHIOU BOR-WEN;YANG CHIN-NING
分类号 H04L9/06;(IPC1-7):H04L9/06 主分类号 H04L9/06
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