| 摘要 |
A radiation tolerant flash memory cell switch includes a programming transistor switch coupled between two circuit nodes to be selectively connected to one another. A floating gate flash memory switch control circuit has a switch-control node coupled to the gate of the programming transistor switch. A sense transistor has a source coupled to the switch-control node, a gate coupled to a word line and a source coupled to a bit line. An addressing circuit is coupled to the word line and the bit line to periodically address the sense transistor. First and second sense amplifiers are coupled to the bit line. The first sense amplifier has a current trip point higher than current trip point of the second sense amplifier. Charge-leakage sensing logic is coupled to the first and second sense amplifiers and configured to generate a charge-leakage threshold signal when the sense transistor is addressed and the second sense amplifier has tripped but the first sense amplifier has not tripped. FPGA programming circuitry is coupled to the floating gate flash memory switch control circuit to reprogram the FPGA in response to the charge-leakage threshold signal.
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