发明名称 Method and system for distributed clock failure protection in a packet switched network
摘要 Protection from a distributed clock failure in a packet switched network device involves monitoring primary clocking information that is received from an input port of the network device, distributing the clocking information to an output port for use in synchronous transmissions, and supplying backup clocking information from within the packet switched network device to the output port if the primary clocking information fails. In an embodiment, the integrity of the primary clocking information is directly monitored in hardware and the backup clocking information is provided by a local clock source that is located within the network device. If a failure in the primary clocking information is detected, the backup clocking information is supplied to the output port from the local clock source. Because the integrity of the primary clocking information is monitored in hardware and because the clock switching is hardware triggered, a clock failure can be identified and corrected in a relatively short period of time, thereby minimizing packet loss during clock failures. In an embodiment, the hardware based failure protection mechanism provides failure protection on a single switch module. In an embodiment, the hardware based failure protection mechanism provides failure protection to a network device that includes multiple switch modules. In an embodiment, a firmware based failure protection mechanism can be programmed to provide a secondary clock from sources other than a local clock source.
申请公布号 AU6330301(A) 申请公布日期 2001.11.26
申请号 AU20010063303 申请日期 2001.05.18
申请人 ENTERASYS NETWORKS, INC. 发明人 DANIEL BERNIER;DEBORAH EDIN;STEWART KENLY
分类号 H04J3/06 主分类号 H04J3/06
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