发明名称
摘要 <p>The specification describes an interconnect strategy for memory chip packages to reduce or eliminate alpha particle contamination from the use of high lead solder interconnections in the vicinity of semiconductor memory cells. In the primary embodiment a high tin solder is recommended. A multi-layer under bump metallization is described that is compatible with high tin solders and flip-chip solder bump technology. <IMAGE></p>
申请公布号 JP3232042(B2) 申请公布日期 2001.11.26
申请号 JP19980144778 申请日期 1998.05.26
申请人 发明人
分类号 H01L21/60;H01L21/822;H01L23/488;H01L23/498;H01L23/556;H01L25/04;H01L25/18;H01L27/04;H01L27/10;(IPC1-7):H01L21/60 主分类号 H01L21/60
代理机构 代理人
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