| 摘要 |
An array of memory cells that includes a plurality of memory cells interconnected via a grid of wordlines and bitlines, wherein each of the bitlines is buried. The array further includes a plurality of contacts, wherein each of the plurality of contacts is formed every N wordlines, N=1, 2, 3, . . . , and wherein each of the plurality of contacts overlies a gate of a different one of the plurality of memory cells. A strap connects one of the buried bitlines to a gate that underlies one of the plurality of contacts and wherein a column of the bitlines has a first discontinuous and a second discontinuous bitline that are separated from one another by a distance DELTA. |
