CLOCK PHASE ADJUSTMENT METHOD, AND INTEGRATED CIRCUIT AND DESIGN METHOD THEREFOR

摘要

The time required for access to a SDRAM (110) is extracted from the layout of an integrated circuit (1000), a first phase difference between an external clock SDCLKO and an internal clock ICLK is calculated, and the value of delay of the external clock signal or the internal clock signal in the integrated circuit (1000) is changed on the basis of the calculated first phase difference, whereby clock phase adjustment for the integrated circuit (1000) in the designing stage is realized. <IMAGE>