| 摘要 |
<p>A variable length decoding apparatus is composed of a memory (22) for storing variable length coded bit data, shifting N-bit data which is previously output according to a control signal by a value of the control signal from the initial bit of the N-bit data, and outputting new N-bit data from a newly initial bit formed due to the shift of the previous N-bit data, a controller (23) for comparing code state values for discriminating a plurality of groups with each other in correspondence to the plurality of the groups for discriminating variable length codes in a variable length code table with each other, with N-bit data which is currently input from the memory (22), determining a group corresponding to the currently output N-bit data, and outputting a control signal for representing the number of bits of the bit data used for the determination of the group according to the determination result, a select signal for representing the determined group and N-bit data just preceding the current N-bit data, a combination logic portion (25) including a plurality of input combinations of which the values are determined by current N-bit data output from the controller (23) and previous N-bit data output from the memory (22) individually corresponding to the plurality of the groups, and generating a plurality of symbols individually corresponding to each group according to values of the individual input combinations and a multiplexer (26) receiving a plurality of the symbols generated by the logic combination portion (25) and outputting symbols selected by a select signal, which can be constituted by simple hardware and give an effect of maintaining a required processing speed for a variable length decoding operation. <IMAGE></p> |
