发明名称 |
Gate etch process for 12 inch wafers |
摘要 |
A method for fabricating a stacked gate array on a semiconductor 12 inch wafer uses a reaction chamber with an upper inductive means and a lower capacitive means. For etching 12 inch wafers the etching parameters are adjusted to values optimised for etching an 8 inch wafer. In particular the power of the upper inductive means is set to a value between 50 and 600 Watts. <IMAGE> |
申请公布号 |
EP1156519(A1) |
申请公布日期 |
2001.11.21 |
申请号 |
EP20000110456 |
申请日期 |
2000.05.16 |
申请人 |
INFINEON TECHNOLOGIES SC300 GMBH & CO. KG |
发明人 |
MORGENSTERN, THOMAS;GREWAL, VIRINDER |
分类号 |
H01L21/28;H01L21/3213 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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