| 摘要 |
automatic control and analog computer engineering; construction of analog computer functional units, analog processors, and the like. SUBSTANCE: parity identifier has character inverter 2 and first relater incorporating comparator 5 whose output is connected to first input of Boolean EXCLUSIVE OR gate 6; second input of the latter functions as control input of first relater and output is connected to control input of make and break switches of comparator 7; outputs of these switches are interconnected to form first-relater output. First and second as well as third and fourth inputs of first relater are connected, respectively, to noninverting and inverting inputs of comparator 5 as well as to inputs of make and break switches of comparator 7. First input of first relater is grounded; third one and interconnected second and fourth inputs are connected, respectively, to output and input of character inverter 3. Newly introduced in identifier are second relater similar to first one, differential amplifier 2, and adder 4. Output and inverting input of differential amplifier 2 are connected, respectively, to input of character inverter 3 and to second input of adder 4; first input and output of the latter are connected, respectively, to output of first relater and to interconnected second and third inputs of second relater whose first and fourth inputs are grounded. Output and control input of second relater connected to control input of first relater function, respectively, as output and control input of parity identifier whose first and second data inputs are formed by inverting and noninverting inputs of differential amplifier 2, respectively. EFFECT: enlarged functional capabilities due to identifying equality of two analog signals varying with time. 1 dwg
|
