发明名称 PLL circuit which can reduce phase offset without increase in operation voltage
摘要 A PLL circuit includes a comparator, an integrator, a phase controller, a current control oscillator and a feedback frequency divider. The comparator compares a phase of an input signal with a phase of a feedback signal to generate a comparison result. The integrator generates a first current to control an oscillation frequency of an output signal based on the comparison result. The phase controller controls a phase of the output signal based on the comparison result such that a phase difference between the phase of the input signal and the phase of the output signal at a lock state is reduced to generate a second current. The current control oscillator generates the output signal. The output signal oscillates at a frequency corresponding to a third current, wherein the first current and the second current add up to the third current. The feedback frequency divider performs a frequency division on the output signal to generate the feedback signal to send to the comparator.
申请公布号 US6320435(B1) 申请公布日期 2001.11.20
申请号 US20000688967 申请日期 2000.10.17
申请人 NEC CORPORATION 发明人 TANIMOTO SUSUMU
分类号 H03L7/093;H03L7/08;H03L7/085;H03L7/089;H03L7/18;(IPC1-7):H03L7/06 主分类号 H03L7/093
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