发明名称 |
For mol integration |
摘要 |
A method of fabricating a semiconductor device in which the bitlines and the bitline contacts are fabricated utilizing a single masking step in which line-space resist patterns are employed in defining the regions for the bitlines and the bitline contacts. The method utilizes a first line-space resist pattern and a second line-space resist pattern which is perpendicularly aligned to the first line-space resist pattern to form bitlines that are self-aligned to the bitline contacts.
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申请公布号 |
US6319840(B1) |
申请公布日期 |
2001.11.20 |
申请号 |
US20000606330 |
申请日期 |
2000.06.29 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
COSTRINI GREGORY;SEITZ MIHEL |
分类号 |
H01L21/60;(IPC1-7):H01L21/302;H01L21/306 |
主分类号 |
H01L21/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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