| 摘要 |
A computer system having a cache for providing data to the system's processing unit(s), wherein the cache controller selectively aborts speculative accesses to its data array. The cache initiates a transfer of data by speculatively transmitting an associated address to the data array, and the data transfer is aborted in response to an intervening determination that the data is to be provided by another source, e.g., by the system memory device (a cache miss) or, in a multi-processor computer wherein the cache is an L3 cache supporting several processing units, by another processing unit which holds the data in a modified state. The data array is arranged in rows and columns, and accessed using a row address strobe (RAS) signal and a column address strobe (CAS) signal. The cache initiates the data transfer by driving a RAS signal associated with the address, and the data transfer is aborted prior to driving a CAS signal associated with the address. The cache registers a state for a memory bank associated with the address, indicating that the memory bank requires a precharge, and later sends a precharge command to the memory bank. By aborting unnecessary data transfers, the L3 data bus is freed up to allow successful speculative access of other cache lines.
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