发明名称 Method for fabricating VLSI devices having trench isolation regions
摘要 A process for fabricating a VLSI device comprising trench isolation regions. The trench isolation regions of a VLSI device is fabricated by a process comprising the following steps: Depositing and patterning pad layers on a substrate to form active regions separated from pad-layer-covered regions; forming side walls at each active region to cover portions of the active region other than its central portion; depositing a first oxide at the space surrounded by the side walls and the central portion of the active region; removing the side walls to form trenches at the active region; and depositing a second oxide on the substrate to fill the trenches and cover the first oxide, the second oxide and the first oxide together forming an oxide trench isolation region.
申请公布号 US6319795(B1) 申请公布日期 2001.11.20
申请号 US20000478125 申请日期 2000.01.05
申请人 MOSEL VITELIC INC. 发明人 LIU JACSON
分类号 H01L21/762;(IPC1-7):H01L21/76 主分类号 H01L21/762
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