发明名称 OFFSET CORRECTING CIRCUIT, OFFSET CORRECTION VOLTAGE GENERATING CIRCUIT AND INTEGRATION CIRCUIT
摘要 PROBLEM TO BE SOLVED: To realize a miniaturized high-accuracy offset correcting circuit of a great time constant in an integrated circuit at a low cost. SOLUTION: An offset voltage outputted from a differential amplifier 1 is sampled/held by a sample/hold(S/H) circuit 6 and inputted to a comparator 7. The comparator 7 compares a reference voltage Vref with the offset voltage and corresponding to a relation between the levels of both the voltages, switch circuits 12 and 13 are driven. One of switch circuits 12 and 13 is turned into conductive state and at a point (c), a voltage fluctuationΔV (ΔV=i×r) to be determined by a current (i) to flow to current sources 10 and 11 and a resistance value (r) of a resistor 14 is generated. Then, thisΔv is integrated by an integration circuit 300 composed of impedance elements 16, 17, 18 and 20, a differential amplifier 19, a reference voltage source 8 and S/H circuits 21 and 22. The integrated result is applied to the non-inverted input terminal of the differential amplifier 1 to become an offset target and offset is corrected.
申请公布号 JP2001320250(A) 申请公布日期 2001.11.16
申请号 JP20000138998 申请日期 2000.05.11
申请人 NEC CORP 发明人 URAYAMA YOJI
分类号 H03F3/45;H03F1/34;H03F3/34;(IPC1-7):H03F3/34 主分类号 H03F3/45
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