SEMICONDUCTOR MEMORY

摘要

PROBLEM TO BE SOLVED: To solve such a problem that the operation speed is difficult to increase for a conventional semiconductor memory while suppressing the area increase of a core part. SOLUTION: A row decoder(RDC) 12 is arranged in each sub-array 11 in a core part 10. Wirings (M2) 13 are arranged along each word line WL on each sub-array 11. The wirings 13 are connected to the word lines WL. A bit line selector(BLS) 14 for selecting a bit line is provided between adjacent sub- arrays 11. A column decoder(CDC) 15 is provided near the bit line selector 14. The bit lines of each sub-array 11 are connected to a main bit line MBL and the main bit line MBL is connected to a sense amplifier arranged in a peripheral circuit region 16.