| 摘要 |
PROBLEM TO BE SOLVED: To provide a CMOS semiconductor integrated circuit capable of decreasing power consumption at standby time without increasing a dedicated power source for reducing the power consumption at the standby time, separately providing a substrate bias generating circuit, which increases the power consumption and a chip area, and forming a triple well structure to become the cause of complicating a process. SOLUTION: This CMOS semiconductor integrated circuit has an internal circuit 2, which is composed of a CMOS transistor, to be functioned in at least two states of an active state to input/output data and a standby state to hold an internal state and an external circuit and is constituted by impressing an inverse bias between the source of any one of P and N channel transistors comprising the internal circuit 2 and a well or substrate while using a power source for external circuit.
|
