发明名称 CIRCUIT AND METHOD FOR STABILIZING D/S CONVERTER
摘要 PROBLEM TO BE SOLVED: To provide a circuit and a method for stabilizing D/S converter, with which the saturation of output characteristics from power amplifiers on the final stage of a D/S converter can be suppressed. SOLUTION: Concerning the stabilizing circuit for D/S converter, with which a reference voltage (Vref) supplied to a transformer (1) is converted and inputted to a quadrant circuit (3) and the output of the quadrant circuit (3) is supplied through a SIN multiplier (4A) and a COS multiplier (4B) to power amplifiers (5A and 5B) on the final stage, this circuit is provided with an AGC circuit (10), which is installed between the transformer (1) and the quadrant circuit (3), for converting the voltage supplied from the transformer (1) to a constant voltage value (V) and supplying it to the quadrant circuit (3) so that sine wave outputs (V0) from the power amplifiers (5A and 5B) on the final stages can not be saturated.
申请公布号 JP2001320248(A) 申请公布日期 2001.11.16
申请号 JP20000140694 申请日期 2000.05.12
申请人 TAMAGAWA SEIKI CO LTD 发明人 KIRYU TAKAKO
分类号 H03F1/34;H03F3/20;(IPC1-7):H03F3/20 主分类号 H03F1/34
代理机构 代理人
主权项
地址