Lateral PNP transistor device, integrated circuit, and fabrication process thereof

摘要

A lateral pnp transistor device comprises a p-type doped semiconductor substrate (10, 41) and a PMOS transistor structure including an n-doped region (41); an n-doped gate region (111, 194) and p-doped source (198) and drain (199) regions; and a buried n+-type doped region (31) located underneath the n-doped region (41). According to the invention the source region is shortened to the gate region and constitutes an emitter of the pnp transistor device; the drain region constitutes a collector of the pnp device; and the n-type doped region constitutes a base of the pnp device. The device includes also a buried p-type doped channel (506) formed in the n-doped region (41), which interconnects the source (198) and drain (199) regions to increase the beta value of the device. The transistor may further comprise a single contact (603) interconnecting the source (198) and gate (194) regions in a self-aligned manner.