Circuit and method for testing an integrated circuit

摘要

A test mode detector (12a) that places a multi-pin integrated circuit (10) in test mode. The test mode detector (12a) comprises a pulse detector (25) that receives a control signal. The control signal controls when the integrated circuit (10) is in test mode. The test mode detector (12a) further includes a latch (27) that is responsive to the pulse detector (25) so as to set the latch (27) when the pulse detector (25) detects a pulse in the control signal that exceeds a threshold level. The latch provides a signal that places the integrated circuit (10) in test mode for a period of time that is greater than the duration of the pulse of the control signal.