| 摘要 |
Input terminals "an", "aw", "as", and "ae" having an identical function and output terminals "bn", "bw", "bs", "be" having an identical function are arranged at the respective sides of a macro cell 1. The input terminals "an", "aw", "as", and "ae" are connected to the input terminals of a NOR circuit 12 and an output from the NOR circuit 12 is supplied to the input terminal "a" of an internal kernel circuit 11. The input terminal to be used is connected by a wire. The other input terminals not to be used are connected to a potential of logical 0 (ground potential). Output buffers 14, 15, 16, and 17 are arranged for the output terminals "bn", "bw", "bs", and "be". A connection wire is provided only for the output terminal to be used. Thus, it is possible to increase the degree of freedom of the macro designing. By isolating the wires to the respective terminals from one another, it is possible to reduce the wire delay, thereby enabling to obtain a high-speed operation.
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