WIRELESS RADIO FREQUENCY TECHNIQUE DESIGN AND METHOD FOR TESTING OF INTEGRATED CIRCUITS AND WAFERS

摘要

A wireless technique for testing of Very Large Scale ICs and wafers is presented. Presented is a test technique that uses standard CMOS without the use of inductors to achieve wireless parametric testing. In terms of existing technologies this system has virtually no area overhead, minimal power requirements and no process or design changes are required. A major feature is that wafer contact is not required. This work shows that a considerable reduction in testing time is possible with this technique. Also presented are specific circuits and simulations showing characteristics of operation under varying conditions. The circuit operation is shown to work down to a 1 volt and sub milliwatt power level at the same time as being 1/10000th the area of a Pentium class VLSI circuit.