| 摘要 |
A dynamic flip-flop includes a first input latch coupled to receive a data input signal and a second input latch coupled to receive the complement of the data input signal. The first input latch has a first shutoff mechanism and the second input latch has a second shutoff mechanism. During a precharge phase, the first and second input latches each provide an output signal. During an evaluation phase, the first and second input latches sample the data input signal and complemented data input signal if a compare enable signal is activated. The shutoff mechanisms as well will then only activate if the compare enable signal is activated. This allows the circuit to save power because flip-flop will not execute a compare during each clock cycle.
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