Memory cell, method of controlling same and method of manufacturing same

摘要

A DRAM memory cell includes a cell transistor (91a) having a source/drain region (6a) connected to a lower electrode (15) of a capacitor (18a) through a pad (10a) and a storage node (11a). During a pause, the lower electrode (15) is not depleted, but at least one of the pad (10a) and the storage node (11a) is depleted to increase a voltage drop therein. The voltage drop alleviates an electric field at a gate end of the transistor (91a) to reduced a TAT (Trap Assisted Tunneling) induced leakage current. The DRAM memory cell is provided which decreases a leakage current from the capacitor and increases time intervals between refresh operations, or refresh pause time.