| 摘要 |
A content addressable memory (CAM) includes non-volatile CAM cells that are in an array similar to a conventional Flash memory array. In the CAM, each word line connects to control gates of Flash memory cells in a row, each bit line connects to drains of Flash memory cells in a column, and each match line is a source line coupled to sources of Flash memory cells in a row. A 2-T CAM cell includes a pair of non-volatile devices coupled to the same word line and match line. Each non-volatile device can be a floating-gate transistor, a Flash memory cell, or a shared-floating-gate (SFG) device. An erase of a CAM word applies erase voltages to the word and match lines associated with the word. The erase does not depend on the bit line voltages. Accordingly, the CAM array can simultaneously perform a search and an erase. With SFG devices, the CAM array can also simultaneously perform a search and a program operation. A CAM buffer stores words to be written in the array and can also conducts a search during an erase so that the CAM can perform back-to-back write and search operations without waiting for completion of an erase operation. A dual CAM cell includes a combination of two CAM elements, each CAM cells being, for example, a known or new 2-T CAM cell. The first element stores a data bit of a CAM word. A second element is programmed to either represent the data bit or a "don't care" state. A search without masking uses the first element in each dual CAM cell, and a search with masking uses some or all of the second elements depending on a mask selection register. To change masking for a particular CAM word, the first element is read, and the second element is reprogrammed according to the value read and the desired masking.
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