| 摘要 |
In a DRAM, a first selector selects one bit of data out of four bits of data read from a memory portion, and provides the data to a data output buffer. Data output buffer is controlled by an output enable signal generated from a determination signal and the like, provides to a data input/output terminal the data from first selector when the four bits of data all match, and causes the data input/output terminal to enter the high impedance state when no match occurs. Since a second selector for selecting either one of read data and determination signal is no longer required, the delay of read data caused by the second selector can be eliminated so that a higher access speed can be achieved.
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