发明名称 Cycle selection circuit and semiconductor memory storage using the same
摘要 The cycle selection circuit according to the present invention has a transfer gate circuit provided with a transfer gate which let an input signal pass through, and a transfer gate which let a standard signal having a standard cycle value pass through, a transfer gate selection circuit which selects one transfer gate from among the transfer gates provided in the transfer gate circuit and outputs the signal that passes through the selected transfer gate as a selected signal, and a forced control signal generating circuit provided in the transfer gate circuit which forcibly selects the transfer gate that let the standard signal pass through and designates the standard signal as a selected signal.
申请公布号 US6316963(B1) 申请公布日期 2001.11.13
申请号 US20000630406 申请日期 2000.08.01
申请人 NEC CORPORATION 发明人 YANAGISAWA TAKESHI
分类号 G11C7/10;G11C11/403;G11C11/406;H03K17/693;(IPC1-7):H03K19/094;H03K19/003 主分类号 G11C7/10
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