| 摘要 |
A pipelined processor is configured to provide virtual single-cycle instruction execution using a register locking mechanism in conjunction with instruction stalling based on lock status. In an illustrative embodiment, a set of register locks is maintained in the form of a stored bit vector in which each bit indicates the current lock status of a corresponding register. A decode unit receives an instruction fetched from memory, and decodes the instruction to determine its source and destination registers. The instruction is stalled for at least one processor cycle if either its source register or destination register is already locked by another instruction. The stall continues until the source and destination registers of the instruction are both unlocked, i.e., no longer in use by other instructions. Before the instruction is dispatched for execution, the destination register of the instruction is again locked, and remains locked until after the instruction completes execution and writes its result to the destination register. The decode unit can thus dispatch instructions to execution units of the processor as if the execution of each of the instructions completed in a single processor cycle, in effect ignoring the individual latencies of the execution units. Moreover, the instructions can be dispatched for execution in a program-specified order, but permitted to complete execution in a different order. |
