发明名称 Method and system for determining critical area for circuit layouts
摘要 A method for computing critical area for opens of a layout, which may be implemented by program storage device readable by machine, tangibly embodying a program of instructions executable by the machine, to perform the method steps includes computing Voronoi diagrams of shapes of the layout, determining core elements and weights for the core elements of the shapes, computing a weighted Voronoi diagram for the layout to arrive at a partitioning of the layout into regions, computing critical area within each region and summing the critical areas to arrive at a total critical area for opens in the layout.
申请公布号 US6317859(B1) 申请公布日期 2001.11.13
申请号 US19990329124 申请日期 1999.06.09
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 PAPADOPOULOU EVANTHIA
分类号 G06F17/50;(IPC1-7):G06F17/50;G06F19/00 主分类号 G06F17/50
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