| 摘要 |
A slot receiving synchronous circuit includes a temporary storage register for temporarily storing receiving slot data having an m-bit fixed length, where m is an integer, a detector for detecting whether the m-bit receiving slot data stored in the temporary storage register has a predetermined pattern, a slot counter circuit, initialized by the detection signal outputted by the detector, for synchronizing the receiving slot data, and a bit counter circuit for counting bit clocks inputted thereto in synchronization with each bit input of the receiving slot data, to provide a count value, and for supplying signals, when the count value reaches a predetermined value, to the slot counter circuit such that the slot counter circuit counts the signals. The slot counter circuit and the bit counter circuit are set to their initial values, respectively, by the detection signal.
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