| 摘要 |
An optical array chip (60) is flip-chip bonded to ASIC substrate (50), and electrically connected to its supporting circuitry through compressively joined solder bump sets (57) and (67). Flowable epoxy hardener material (70) is applied to underfill between the surfaces of chip (60) and the ASIC surface, surrounding the bump contact sets and filling a standoff cavity system that had been etched in the electrical interface side of chip (60) to a depth greater than electrical layer (66) of chip (60) by the amount of the pre-determined standoff height, prior to application of its bump contacts. Standoff grid (72) and individual optical devices (69) are exposed after lapping and etching of the optical interface side of chip (60) down to the level of electrical layer (66). The grid structure may have other forms, such as a vertical perimeter standoff ridge surrounding chip (60) or penetrating electrical layer (66), or a distributed pattern of vertical posts or wall sections penetrating electrical layer (66). |
