| 摘要 |
PURPOSE: A circuit configuration and device is provided to offer a circuit configuration having a variable number of data outputs and a device for reading out data from the circuit configuration with the variable number of data outputs so that data can be read out of a serially readable data memory via a freely selectable number of existing data outputs and the serial data are routed with a delay effected by memory/delay circuits to a plurality of data outputs. CONSTITUTION: The device comprises a shift register(1), memory/delay circuits(3, 5, 6), a control circuit(9), a clock circuit(8), a clock line(10), an output line(11), and a control lines(14). The shift register(1) represents a serial data memory. The shift register(1) is connected via the first control line(14) to the control circuit(9), via the first data line(11) to the first data output(2) and to the first memory/delay circuit(3). The control circuit(9) has a control input(17), by which the control circuit(9) can be switched to a read-out mode. The first memory/delay circuit(3) is connected by a data output to the second memory/delay circuit(5) via the second data line(12) and to the second data output(4). The second memory/delay circuit(5) is connected via the third data line(15) to the third data output(16) and to the third memory/delay circuit(6). The third memory/delay circuit(6) is connected to the fourth data output(7) via the fourth data line(13). The first, second, third and fourth data outputs(2, 4, 16, 7) are embodied, for example, as terminal pins of a semiconductor memory module(70). The first, second and third memory/delay circuits(3, 5, 6) are preferably embodied as master/slave flip-flops. However, any other type of memory/delay circuit by which data present at the input are output at the output delayed by a pre-definable time can also be used.
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