| 摘要 |
PURPOSE: An apparatus for interfacing a TD-bus and a P-bus using a main processor is provided to simplify hardware by making a main processor allocate SCC channels and control P-bus communication. CONSTITUTION: A TD-bus interface(108) executes connection or disconnection with a TD-bus. A P-bus interface(106) executes connection or disconnection with a P-bus. A main processor(100), occupying a local bus using a plurality of SCC channels, receives data from the local bus and stores the data in a local memory(102). The main processor(100) reads data from the local memory(102) and outputs the data to the TD-bus interface(108). The main processor(100) outputs control data through the local bus in order to communicate with the P-bus. In the event that a fault is generated in the middle of IPC communication with the P-bus through the P-bus interface(106), the main processor controls an Ethernet interface(110) for IPC circuitous communication. The local memory(102) stores the control data of the main processor(100) and the data generated in its control operations. A control logic(104) outputs an access grant signal for the local memory(102) and connection/disconnection control signals for the TD-bus interface(108) and the P-bus interface(106). The Ethernet interface(110), in case that a fault is generated in the middle of IPC communication with the P-bus, executes control for IPC circuitous communication by connecting an Ethernet bus. A ROM(103) stores the initializing data of each processor.
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