| 摘要 |
PURPOSE: A fabrication method of a CMOS(Complementary MOS) transistor is provided to reduce a parasitic capacitance and to improve an integration degree of the transistors by forming a contact plug on a polysilicon layer. CONSTITUTION: After forming an n-well(102) in a substrate(100), a field oxide(104) is formed at an isolation region of the substrate. After forming a gate electrode(108a) on an active region, LDD(Lightly Doped Drain) regions(110a,110b) are formed at an NMOS and a PMOS transistor regions(A,B), respectively. An insulating spacer(112) is formed at both sidewalls of the gate electrode(108a). After forming a second polysilicon film(114) on the resultant structure, the second polysilicon film(114) is then selectively etched. N-type impurities and p-type impurities are sequentially implanted into the NMOS and the PMOS transistor regions(A,B), respectively. An annealing is carried out, so that n+ source and drain regions(122a) and p+ source and drain regions(122b) are self-aligned.
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