发明名称 Scalable architecture for multiply/accumulate unit
摘要 <p>A data processing device which includes an input unit (400) programmable to receive data in parallel or serial format and to output the received data to a processing unit (50) in parallel. The processing unit (50) performs multiply and accumulate operations on data in accordance with a predefined coefficient and outputs the processed data to a switching unit (500) programmable to route the processed data. &lt;IMAGE&gt;</p>
申请公布号 EP1152346(A2) 申请公布日期 2001.11.07
申请号 EP20010102902 申请日期 2001.02.07
申请人 HEWLETT-PACKARD COMPANY 发明人 CRANE, RANDY T.
分类号 G06F7/52;G06F7/523;G06F7/53;G06F17/10;(IPC1-7):G06F17/14 主分类号 G06F7/52
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