发明名称 |
Simultaneous bumping/bonding process utilizing edge-type conductive pads and device fabricated |
摘要 |
A method for simultaneous bumping/bonding an IC chip to a semiconductor substrate and a semiconductor package fabricated by the method are described. In the method, a plurality of edge-type conductive pads formed of under-bump-metallurgy layers are first fabricated on an IC chip by dicing through conductive pads formed on a silicon wafer. The edge-type conductive pads, or UBM layer, are then positioned in close proximity to conductive elements formed on a top surface of a semiconductor substrate. A volume of solder is then applied to the interface between the conductive pads and the conductive elements to form electrical bonds between the two. A suitable method for applying the volume of solder may be a solder jetting technique, a solder printing technique or a method utilizing pre-applied solder paste on the surfaces to be bonded together. The present invention method allows a multiplicity of IC chips equipped with edge-type conductive pads to be fabricated by dicing a silicon wafer through conductive pads formed on a top surface. A multiplicity of IC chips can be fabricated at low fabrication cost. The method further provides the benefit that an IC chip may be bonded to a semiconductor substrate in either a face-up or a face-down position. This is made possible by the conductive pads formed on the vertical edges of the IC chip which connect to conductive elements formed on a semiconductor substrate.
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申请公布号 |
US6312974(B1) |
申请公布日期 |
2001.11.06 |
申请号 |
US20000699128 |
申请日期 |
2000.10.26 |
申请人 |
INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE |
发明人 |
WU EN-BOA;CHU TSUNG-YAO;HUANG HSIN-CHIEN |
分类号 |
H01L21/60;(IPC1-7):H10L21/44;H10L21/48;H10L21/50 |
主分类号 |
H01L21/60 |
代理机构 |
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主权项 |
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地址 |
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