| 摘要 |
A storage device which can perform a refresh on a semiconductor memory with a small sized configuration, including a timing generation circuit of a DRAM which requires a refresh for retaining the memory, a memory access circuit for accessing a line buffer memory, a refresh control circuit for control so that an indicated number of refreshes of the line buffer memory is performed within a predetermined interval, and a CPU for monitoring the accessing load to the line buffer memory by the memory access circuit, determining the number of refreshes within the predetermined interval based on the load, and instructing the determined number to the refresh control circuit.
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