发明名称 Apparatus and method for maintaining cache coherency in a memory system
摘要 According to one embodiment, a computer system is disclosed. The computer system includes a processor, a memory, an inverting device, a storage device coupled to the inverting device and a device coupled to the storage device. The device receives byte enable information and inverted information and provides inverted byte enable information to the memory upon a write back operation to the memory.
申请公布号 US6314497(B1) 申请公布日期 2001.11.06
申请号 US19980205646 申请日期 1998.12.03
申请人 INTEL CORPORATION 发明人 CLOHSET STEVE J.;KHANDEKAR NARENDRA S.;BOGIN ZOHAR
分类号 G06F12/08;(IPC1-7):G06F12/12 主分类号 G06F12/08
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