发明名称 |
Parallel/pipeline VLSI architecture for a low-delay CELP coder/decoder |
摘要 |
An integrated circuit for processing a speech signal in accordance with a CELP standard includes a plurality of processing elements coupled to a data bus in parallel. Each processing element includes a multiplier and an accumulator. The integrated circuit further includes an auxiliary processing element, which is also coupled to the data bus and has a division unit and a comparator. The plurality of processing elements and the auxiliary processing element are also coupled in a pipeline formation.
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申请公布号 |
US6314393(B1) |
申请公布日期 |
2001.11.06 |
申请号 |
US19990270918 |
申请日期 |
1999.03.16 |
申请人 |
HUGHES ELECTRONICS CORPORATION |
发明人 |
ZHENG YUE-PENG;PATEL SHVETAL K.;SWAMINATHAN KUMAR |
分类号 |
G10L19/12;G10L19/14;(IPC1-7):G10L19/12 |
主分类号 |
G10L19/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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