| 摘要 |
An interval timer for timing multiple repetitive timing intervals. A single large clock register increments ticks of a high-speed clock. Successive previously-stored timing values are loaded into a single compare register which is preferably of equivalent length to the clock register. A comparator monitors the clock register's current value and compares it with the timing value currently loaded in the compare register. As the clock register's value reaches the current timing value in the compare register, an alert signal is generated and sent out to activate a particular timed operation identified by an event ID ("EID") associated with the timing value in the compare register. The current timing value in the compare register is then discarded, and the next timing value in sequence is retrieved into the compare register. A repeat flag is carried with each timing value and associated EID. If the flag is set, the system recognizes the corresponding timing value as a repetitive interval timing value. Upon recognizing the repeat flag as set, the inventive mechanism refers to a separate repeat value lookup table indexed by EID. The mechanism retrieves the repeat value associated with the EID of the timing value just reached, adds this repeat value to the timing value just reached, and then inserts the resulting sum into the stack as a new timing value associated with the repeated EID.
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