发明名称 |
Fast accessible semiconductor memory device |
摘要 |
A memory array is divided into a plurality of memory sub blocks in row and column directions. A column selection line is provided in the column direction in a region between blocks. A block decoding circuit generating a local column selection signal is arranged corresponding to each of the memory sub blocks. A main I/O line pair group is provided for each of the memory sub blocks and each column of the memory sub block is connected to the corresponding main I/O line pair in accordance with the local column selection line. Thus, data with a desired bit width can be produced without any increase in area occupied by the array nor decrease in the speed of column access.
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申请公布号 |
US6314042(B1) |
申请公布日期 |
2001.11.06 |
申请号 |
US19980181675 |
申请日期 |
1998.10.29 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
TOMISHIMA SHIGEKI;OOISHI TSUKASA;KATO HIROSHI |
分类号 |
G11C7/10;G11C8/12;G11C11/4097;(IPC1-7):G11C8/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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